L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide
ID
683667
Date
9/13/2024
Public
1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Document Revision History
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Troubleshooting and Observing the Link Status
2.1. Design Components
2.2. Hardware and Software Requirements
2.3. Directory Structure
2.4. Generating the Design Example
2.5. Simulating the Design Example
2.6. Compiling the Design Example and Programming the Device
2.7. Installing the Linux Kernel Driver
2.8. Running the Design Example Application
7.1.1. Register Access Definitions
7.1.2. PCI Configuration Header Registers
7.1.3. PCI Express Capability Structures
7.1.4. Intel Defined VSEC Capability Header
7.1.5. Uncorrectable Internal Error Status Register
7.1.6. Uncorrectable Internal Error Mask Register
7.1.7. Correctable Internal Error Status Register
7.1.8. Correctable Internal Error Mask Register
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers
7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules
7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
7.2.1.5. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure
10.5.2. ebfm_barwr_imm Procedure
10.5.3. ebfm_barrd_wait Procedure
10.5.4. ebfm_barrd_nowt Procedure
10.5.5. ebfm_cfgwr_imm_wait Procedure
10.5.6. ebfm_cfgwr_imm_nowt Procedure
10.5.7. ebfm_cfgrd_wait Procedure
10.5.8. ebfm_cfgrd_nowt Procedure
10.5.9. BFM Configuration Procedures
10.5.10. BFM Shared Memory Access Procedures
10.5.11. BFM Log and Message Procedures
10.5.12. Verilog HDL Formatting Functions
1.9. Channel Availability
PCIe Hard IP Channel Restrictions
Each L- or H-Tile transceiver tile contains one PCIe Hard IP block. The following table and figure show the possible PCIe Hard IP channel configurations, the number of unusable channels, and the number of channels available for other protocols. For example, a PCIe x4 variant uses 4 channels and 4 additional channels are unusable.
PCIe Hard IP Configuration | Number of Unusable Channels | Usable Channels |
---|---|---|
PCIe x1 | 7 | 16 |
PCIe x2 | 6 | 16 |
PCIe x4 | 4 | 16 |
PCIe x8 | 0 | 16 |
PCIe x16 | 0 | 8 |
Note: The PCIe Hard IP uses at least the bottom eight Embedded Multi-Die Interconnect Bridge (EMIB) channels, no matter how many PCIe lanes are enabled. Thus, these EMIB channels become unavailable for other protocols.
Figure 11. PCIe Hard IP Channel Configurations Per Transceiver Tile
The table below maps all transceiver channels to PCIe Hard IP channels in available tiles.
Tile Channel Sequence | PCIe Hard IP Channel | Index within I/O Bank | Bottom Left Tile Bank Number | Top Left Tile Bank Number | Bottom Right Tile Bank Number | Top Right Tile Bank Number |
---|---|---|---|---|---|---|
23 | N/A | 5 | 1F | 1N | 4F | 4N |
22 | N/A | 4 | 1F | 1N | 4F | 4N |
21 | N/A | 3 | 1F | 1N | 4F | 4N |
20 | N/A | 2 | 1F | 1N | 4F | 4N |
19 | N/A | 1 | 1F | 1N | 4F | 4N |
18 | N/A | 0 | 1F | 1N | 4F | 4N |
17 | N/A | 5 | 1E | 1M | 4E | 4M |
16 | N/A | 4 | 1E | 1M | 4E | 4M |
15 | 15 | 3 | 1E | 1M | 4E | 4M |
14 | 14 | 2 | 1E | 1M | 4E | 4M |
13 | 13 | 1 | 1E | 1M | 4E | 4M |
12 | 12 | 0 | 1E | 1M | 4E | 4M |
11 | 11 | 5 | 1D | 1L | 4D | 4L |
10 | 10 | 4 | 1D | 1L | 4D | 4L |
9 | 9 | 3 | 1D | 1L | 4D | 4L |
8 | 8 | 2 | 1D | 1L | 4D | 4L |
7 | 7 | 1 | 1D | 1L | 4D | 4L |
6 | 6 | 0 | 1D | 1L | 4D | 4L |
5 | 5 | 5 | 1C | 1K | 4C | 4K |
4 | 4 | 4 | 1C | 1K | 4C | 4K |
3 | 3 | 3 | 1C | 1K | 4C | 4K |
2 | 2 | 2 | 1C | 1K | 4C | 4K |
1 | 1 | 1 | 1C | 1K | 4C | 4K |
0 | 0 | 0 | 1C | 1K | 4C | 4K |
PCIe Soft IP Channel Usage
PCI Express soft IP PIPE-PHY cores available from third-party vendors are not subject to the channel usage restrictions described above. Refer to Intel FPGA PCI Express IP Support Center for more information about soft IP cores for PCI Express.