L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 3/05/2024
Document Table of Contents Resets

The PCIe Hard IP generates the reset signal. The Avalon-MM DMA bridge has a single, active low reset input. It is a synchronized version of the reset from the PCIe IP core.
Figure 47. Clock and Reset Connections
Table 44.  Resets




app_nreset_status Output This is active low reset signal. It is derived from npor or pin_perstn. You can use this signal to reset the Application.
currentspeed[1:0] Output

Indicates the current speed of the PCIe link. The following

encodings are defined:
  • 2'b00: Undefined
  • 2'b01: Gen1
  • 2'b10: Gen2
  • 2'b11: Gen3


The Application Layer drives this active low reset signal. npor resets the entire IP core, PCS, PMA, and PLLs. npor should be held for a minimum of 20 ns. This signal is edge, not level sensitive; consequently, a low value on this signal does not hold custom logic in reset. This signal cannot be disabled.


Active low reset from the PCIe reset pin of the device. Resets the datapath and control registers.
ninit_done Input This is an active-low asynchronous input. A "1" on this signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode. To use the ninit_done input, instantiate the Reset Release Intel FPGA IP in your design and use its ninit_done output to drive the input of the Avalon® memory mapped IP for PCIe.