L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 3/05/2024
Document Table of Contents

9.3. Receiving a Non-Posted Completion TLP

The TLPs associated with the non-posted TX requests are stored in the RP RX FIFO buffer and subsequently loaded into RP_RX_REG/STATUS registers. The Application Layer performs the following sequence to retrieve the TLPs:
  1. Polls the RP_RX_STATUS.SOP bit to determine when it is set to 1’b1.
  2. If RP_RX_STATUS.SOP = 1’b’1, reads RP_RX_REG to retrieve the first dword of the TLP.
  3. Reads the RP_RX_STATUS.EOP bit.
    • If RP_RX_STATUS.EOP = 1’b0, reads RP_RXCPL_REG to retrieve the next dword of the TLP, then repeats this step.
    • If RP_RX_STATUS.EOP = 1’b1, reads RP_RXCPL_REG to retrieve the final dword of the TLP.