L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 3/05/2024
Document Table of Contents

7.1.2. PCI Configuration Header Registers

The Correspondence between Configuration Space Registers and the PCIe Specification lists the appropriate section of the PCI Express Base Specification that describes these registers.

Figure 49. Configuration Space Registers Address Map
Figure 50. PCI Configuration Space Registers - Byte Address Offsets and Layout