L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 3/05/2024
Document Table of Contents

4. Parameters

This chapter provides a reference for all the parameters of the Intel L-/H-Tile Avalon-ST for PCI Express IP core.
Table 13.  Design Environment ParameterStarting in Quartus® Prime 18.0, there is a new parameter Design Environment in the parameters editor window.




Design Environment



Identifies the environment that the IP is in.

  • The Standalone environment refers to the IP being in a standalone state where all its interfaces are exported.
  • The System environment refers to the IP being instantiated in a Platform Designer system.
Table 14.  System Settings




Application Interface Type


Selects the interface to the Application Layer.

Application Interface Width


Selects the width of the interface to the Application Layer. Currently, the only option available for this interface width is 256-bit .
Note: DMA operations are only supported when this parameter is set to 256-bit.
Hard IP Mode

Gen3x8, 256-bit interface, 250 MHz

Gen3x4, 256-bit interface, 125 MHz

Gen3x2, 256-bit interface, 125 MHz

Gen3x1, 256-bit interface, 125 MHz

Gen2x16, 256-bit interface, 250 MHz

Gen2x8, 256-bit interface, 125 MHz

Gen2x4, 256-bit interface, 125 MHz

Gen2x2, 256-bit interface, 125 MHz

Gen2x1, 256-bit interface, 125 MHz

Gen1x16, 256-bit interface, 125 MHz

Gen1x8, 256-bit interface, 125 MHz

Gen1x4, 256-bit interface, 125 MHz

Gen1x2, 256-bit interface, 125 MHz

Gen1x1, 256-bit interface, 125 MHz

Selects the following elements:

  • The lane data rate. Gen1, Gen2, and Gen3 are supported
  • The Application Layer interface frequency

The width of the data interface between the hard IP Transaction Layer and the Application Layer implemented in the FPGA fabric.

Note: If the Mode selected is not available for the configuration chosen, an error message displays in the Message pane.
Port type

Native Endpoint

Root Port

Specifies the port type.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configuration Space.

A Root Port testbench is not available in the current release. If you select the Root Port, you have to create your own testbench.