Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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6. Troubleshooting Guidelines

GPIO Debug Guidelines

The following table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when designing GPIO systems with Intel® Agilex™ devices. These debug guidelines are just initial debug actions and do not necessarily resolve the failures in your designs.
Table 82.  GPIO Debug Guidelines
Failure Symptoms Recommended Debug Actions

1.2 V LVCMOS output at the entire bank does not reach 1.2 V.

  • Check the power-up and power-down sequences of each voltage rail with respect to time.
  • Compare the power sequences as per recommendation in the Intel® Agilex™ Power Management User Guide.
  • Verify the VCCIO_PIO voltage signal is 1.2 V.

Intel® Quartus® Prime software shows an error message to indicate incorrect I/O settings for VCCIO during design compilation.

Error message example: Illegal constraint of I/O bank to the location <I/O bank>

Select the I/O pins specified in the error message and check the I/O settings for the pins.

Intel® Quartus® Prime software shows illegal I/O error message during design compilation.

Error message example: Programmable VOD option is set to 1 for pin <pin_name>, but setting is not supported by <I/O standard>

Select the I/O pins specified in the error message and set the pins to the correct I/O function. Refer to the device pin-outs file for more information about the pin functions.

Unable to configure a pin as an open-drain output pin.

  • Ensure that the pin is set to the correct voltage specification per the device data sheet.
  • To ensure the pin is correctly set to open-drain output, check the compilation report or the resource property editor.

Unable to configure a pin to use the bus-hold feature.

Ensure that the pin is not set to programmable pull-up resistor. The bus-hold feature is not available when the pin is set to programmable pull-up resistor.

High-Speed SERDES I/O Debug Guidelines

The following table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when designing high-speed SERDES systems with Intel® Agilex™ devices. These debug guidelines are just initial debug actions and do not necessarily resolve the failures in your designs.
Table 83.  High-speed SERDES I/O Debug Guidelines
Failure Symptoms Recommended Debug Actions

pll_locked signal is unable to assert

  • Ensure that the pll_areset signal is deasserted.
  • If you are using the LVDS SERDES IP with external PLL mode, ensure that the desired PLL IP settings match the recommended settings from the LVDS SERDES IP summary tab.
    Note: Use simple PLL settings when debugging this failure to limit the failure scope. Ensure that the external PLL automatic switchover and dynamic reconfiguration modes are disabled.
  • Switch to use internal PLL to verify if the same failure occurs when using internal PLL.

rx_dpa_locked signal is unable to assert

  • Ensure that the pll_locked signal is asserted and the rx_dpa_reset is deasserted. It is important to ensure that the PLL is able to lock to confirm that the LVDS SERDES IP input clock frequency is correct.
  • Provide a training pattern to the DPA block with a toggling signal that conforms to the LVDS input buffer specification.

Random bit error occurs at LVDS RX parallel data out bus

  • Ensure that RD termination is applied. You can enable OCT RD using the assignment editor in the Intel® Quartus® Prime software or place an on-board 100 Ω resistor termination. Refer to the True Differential Signaling I/O Termination section for more details on termination implementation.
  • Measure the rx_in_p and rx_in_n signal voltages and ensure that the voltages conforms to the VID and VICM requirements.
  • If the rx_in_p and rx_in_n signals have jitter, ensure that the signals have sufficient data valid window that conforms to the sampling window requirements.
  • Re-initialize the LVDS RX reset sequence and ensure that:
    • The pll_locked signal is asserted.
    • The rx_dpa_locked signal is asserted.
    • The rx_fifo_reset signal is deasserted after FIFO reset (for DPA FIFO mode only).
    • The rx_divfwdclk (soft-CDR mode only) and rx_coreclock signals have the correct clock frequencies ( ).

LVDS RX parallel data out is not matching a training pattern

Assert the rx_bitslip_ctrl signal for one clock cycle to add bit latency to the received bitstream. Continue to assert the signal until you see the expected pattern at the rx_out bus.

The rx_bitslip_max signal asserts before it reaches the Bitslip rollover value

  • Check the bitslip rollover value in the LVDS SERDES IP. Set the rollover value based on .
  • Assert the rx_bitslip_reset signal before starting the bit slip and the reset must hold for at least one parallel clock cycle (based on rx_coreclock or rx_divfwdck).

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