Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.2. Using LVDS SERDES Intel FPGA IP for High-Speed LVDS I/O Implementation

The Intel® Quartus® Prime software provides the LVDS SERDES Intel FPGA IP for you to implement your high-speed LVDS I/O design. The IP provides the following features for you to implement your LVDS I/O design:
  • Parameterizable data channel widths
  • Parameterizable SERDES factors
  • Registered input and output ports
  • PLL control signals
  • Non-DPA mode
  • DPA mode
  • Soft clock data recovery (CDR) mode
  • Clock phase alignment (CPA) block
You can implement the following usage modes using the IP:
  • Transmitter—select the TX parameter to generate the IP as transmitter mode.
  • Non-DPA receiver—select the RX Non-DPA parameter to generate the IP as non-DPA receiver mode.
  • DPA receiver—select the RX DPA-FIFO parameter to generate the IP as DPA receiver mode.
  • Soft CDR receiver—select the RX Soft-CDR parameter to generate the IP as soft-CDR receiver mode.
Each I/O sub-bank can support one IP instance with a maximum of 12 transmitter or receiver channels. For designs with more than 12 channels, you must generate a new IP instance and place it in a new I/O sub-bank. The following table list the supported number of IP instances according to the usage modes and PLL configurations for one I/O sub-bank.
Table 50.  Supported Usage Modes with Number of IP Instances in an I/O Sub-bank
Number of Channels Usage Modes PLL Configuration Number of IP Instances
1–24 (maximum of 12 transmitter and 12 receiver channels) Transmitters and receivers External PLL 2
1-12 Transmitters External PLL 1
Internal PLL 1
1-12 Receivers External PLL 1
Internal PLL 1