4.8.3. Timing Analysis for the External PLL Mode
Some of the SERDES constraints are derived from the PLL clocks. Therefore, the external PLL clock settings must be generated before the LVDS SERDES IP clock settings. In your project's .qsf, ensure that the line for the IOPLL IP's .qip appears before the line for the LVDS SERDES IP's .qip.
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