4.7. Intel® Agilex™ LVDS SERDES Source-Synchronous Timing Budget
The LVDS SERDES enables high-speed transmission of data, resulting in better overall system performance. To take advantage of fast system performance, you must analyze the timing for these high-speed signals. Timing analysis for the differential block is different from traditional synchronous timing analysis techniques.
The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead of the clock-to-output setup times. High-speed differential data transmission requires the use of timing parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.
This section defines the source-synchronous differential data orientation timing parameters, the timing budget definitions for Intel® Agilex™ devices, and how to use these timing parameters to determine the maximum performance of a design.
Did you find the information on this page useful?