Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

The OCT IP can generate a design example that matches the same configuration chosen for the IP.

The design example is a simple design that does not target any specific application. You can use the design example as a reference on how to instantiate the IP.

To generate the design example files, turn on the Generate Example Design option in the Generation dialog box during IP generation.

Note: The OCT IP does not support VHDL generation.
  • The software generates the <instance>_example_design directory along with the IP, where <instance> is the name of your IP.
  • The <instance>_example_design directory contains the make_qii_design.tcl scripts.
Note: The .qsys files are for internal use during design example generation only. You cannot edit the files.

Generating the Intel Quartus® Prime Design Example

The make_qii_design.tcl script generates a synthesizable design example along with an Intel® Quartus® Prime project, ready for compilation.
To generate a synthesizable design example, follow these steps.
  1. After generating the IP together with the design example files, run the following script at the command prompt: quartus_sh -t make_qii_design.tcl.
  2. If you want to specify an exact device to use, use the following command: quartus_sh -t make_qii_design.tcl <device_name> .
The script generates a qii directory that contains the ed_synth.qpf project file. You can open and compile this project in the Intel® Quartus® Prime software.

Did you find the information on this page useful?

Characters remaining:

Feedback Message