Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents LVDS SERDES IP Transmitter Settings

Table 59.  Transmitter Settings Tab
Parameter Condition Value Default Description
Enable tx_coreclock port Functional mode = TX

Use external PLL = Off

On, Off On

Turn on to expose the tx_coreclock port that you can use to drive the core logic feeding the transmitter.

Intel recommends that you use the tx_coreclock output signal if it is requested.

Note: To expose the tx_coreclock when using external PLL, turn off Use external PLL option before turning on the Enable tx_coreclock port. After making changes to Enable tx_coreclock port, you can turn Use external PLL back on.
Enable tx_outclock port Functional mode = TX On, Off On

Turn on to expose the tx_outclock port.

  • The tx_outclock port frequency depends on the setting for the Tx_outclock division factor parameter.
  • The phases of the tx_outclock_p and tx_outclock_n ports depend on the Desired tx_outclock phase shift parameter.

Turning on this parameter reduces the maximum number of channels per TX interface by one channel.

Desired tx_outclock phase shift (degrees) Functional mode = TX
  • 0
  • 180
  • 360
0 Specifies the phase relationship between the outclock and outgoing serial data in degrees of the LVDS fast clock.
Actual tx_outclock phase shift (degrees) Depends on the Desired tx_outclock phase shift (degrees) input. Refer to related information. 0

Displays the closest achievable tx_outclock phase shift to the desired tx_outclock phase shift.

Tx_outclock division factor Functional mode = TX Depends on the SERDES factor input. 2 Specifies the ratio of the fast clock frequency to the tx_outclock frequency. For example, the maximum number of serial transitions per tx_outclock cycle.