Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.3.5.1. Setting the Transmitter Output Clock Parameters

The Clock Resource Summary tab lists the required frequencies, phase shifts, duty cycles of the required clocks, instructions for connections, and compensation mode that you need to set in the IOPLL Intel® FPGA IP. You can refer to this tab for information about configuring and connecting an external PLL to the LVDS SERDES IP.

You can specify the relationship of tx_outclock to the tx_out data using these parameters:

  • Desired tx_outclock phase shift (degrees)
  • Tx_outclock division factor

The parameters set the phase and frequency of the tx_outclock based on the fast_clock, which operates at the serial data rate. You can set the tx_outclock frequency using the available division factors from the drop-down list.

Edge-Aligned tx_outclock to tx_out

For rising tx_outclock edge-aligned to the MSB of the serial data on tx_out, specify 0° phase shift.

Figure 58.  0° Edge Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8


Center-Aligned tx_outclock to tx_out

To specify the center-aligned relationship between tx_outclock and the MSB of the serial data on tx_out, specify a 180° phase shift.

Figure 59.  180° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 8


  • Phase shift values from 0° to 315° position the rising edge of tx_outclock within the MSB of the tx_out data.
  • Phase shift values starting from 360° position the rising edge of tx_outclock in serial bits after the MSB. For example, a phase shift of 540° positions the rising edge in the center of the bit after the MSB.
Figure 60.  180° Center Aligned tx_outclock x8 Serializer Waveform with Division Factor of 2This figure shows a x8 serialization factor using a 180° phase shift with a tx_outclock division factor of 2 (DDR clock and data relationship).


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