4.4.1. LVDS SERDES Receiver Blocks
The receiver has a differential buffer and I/O PLLs that you can share among the transmitter and receiver, a DPA block, a synchronizer, a data realignment block, and a deserializer. The True Differential Signaling buffer can receive LVDS, mini-LVDS, RSDS, and LVPECL compatible signaling. You can statically set the I/O standard of the receiver pins to True Differential Signaling in the Intel® Quartus® Prime software Assignment Editor or .qsf file.
|Dedicated Circuitry / Feature||Description|
|Differential I/O buffer||Supports True Differential Signaling compatible with LVDS, RSDS, Mini-LVDS, and LVPECL|
|SERDES||Up to 10-bit wide deserializer|
|Phase-locked loops (PLLs)||Generates different phases of a clock for data synchronizer|
|Data realignment (Bit slip)||Inserts bit latencies into serial data|
|DPA||Chooses a phase closest to the phase of the serial data|
|Synchronizer (FIFO buffer)||Compensate for phase differences between the data and the receiver’s input reference clock|
|On-chip termination (OCT)||100 Ω in True Differential Signaling I/O standards|
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