Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents

4.1. Intel® Agilex™ High-Speed SERDES I/O Overview

Intel® Agilex™ devices support LVDS serializer/deserializer (SERDES) through the True Differential Signaling I/O banks.

These devices support SERDES on all True Differential Signaling I/O banks with the following features:

  • Differential 100-ohm OCT RD.
  • Differential I/O reference clock for the I/O PLL that drives the SERDES.
  • Dedicated transmitter and dedicated receiver differential pin pairs in each I/O bank with multiple usage modes options.
  • 24 receiver channels with SERDES and DPA, and 24 transmitter channels with SERDES in each I/O bank. The total of SERDES channel count varies among Intel® Agilex™ devices depending on the total pins available in the package.
Table 48.  Usage Modes Summary of the Intel® Agilex™ High-Speed SERDESAll usage modes in this table support SERDES factors of 3 to 10.
Functional Mode Description



In the transmitter mode, the SERDES block acts as a serializer.

A PLL generates the following signals:

  • fast_clock
  • load_enable

Non-DPA Receiver

(RX Non-DPA)

In the RX non-DPA mode, The SERDES block acts as a deserializer that bypasses the DPA and DPA-FIFO.

A PLL generates the fast_clock signal. Because the incoming data is captured at the bitslip with the fast_clock signal, you must ensure the correct clock–data alignment.

DPA-FIFO Receiver


In the RX DPA-FIFO mode, the SERDES block acts as a deserializer that uses the DPA block.

The DPA block uses a set of eight DPA clocks to select the optimal phase for sampling data. These DPA clocks run at the fast_clock frequency with each clock phase-shifted 45° apart. The DPA-FIFO, a circular buffer, samples the incoming data with the selected DPA clock and forwards the data to LVDS clock domain. The bitslip circuitry then samples the data and inserts latencies to realign the data to match the desired word boundary of the deserialized data.

Soft-CDR Receiver

(RX Soft-CDR)

In the RX soft-CDR mode, the IP forwards the optimal DPA clock (DPACLK) into the LVDS clock domain as the fast_clock signal. The IP forwards the rx_divfwdclk, produced by the local clock generator to the core.

Each bank has only 12 soft-CDR channels available.

To find out which pin pairs can support soft-CDR channels in each bank, refer to the device pin-out files. In the device pin-out files, the "Dedicated Tx/Rx Channel" column lists the available LVDS pin pairs in an LVDS<bank number>_<pin pair> <p or n> format. If the value of <pin pair> is an even number, the pin pair supports soft-CDR mode.