Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.4. I/O Implementation Guide

The Intel® Quartus® Prime software provides the following tools for you to create, configure and compile your I/O design:
  • Assignment editor
  • Pin planner
  • GPIO Intel FPGA IP

Each tool provides different functions and supports different features to implement your I/O design.

Table 15.  Assignment Editor, Pin Planner, and GPIO Intel FPGA IP Descriptions
Tools Description Supported IOE Features/ I/O Assignment Supported I/O Standards
Assignment Editor You can view, create and edit assignments with this tool. The Intel® Quartus® Prime software dynamically validates changes that you make through the editor and issues errors or warnings for invalid assignments.
  • Programmable open-drain output
  • Programmable slew rate control
  • Programmable I/O delay
  • Programmable bus-hold
  • Programmable weak pull-up resistor
  • Programmable pre-emphasis
  • Programmable VOD
  • OCT
  • 1.2 V LVCMOS
  • SSTL-12
  • HSTL-12
  • POD12
  • HSUL-12
  • Differential SSTL-12
  • Differential HSTL-12
  • Differential HSUL-12
  • Differential POD-12
  • True Differential Signaling
Pin Planner Provides a graphical representation of the pin locations of an Intel® Agilex™ device. This tool allows you to do initial pin planning for your device. You can locate, place, and make assignments to the I/O pins using this tool. You can also configure board trace models for the pins you selected to use in signal integrity reports.
  • Programmable slew rate control
  • Programmable bus-hold
  • Programmable weak pull-up resistor
  • OCT
  • 1.2 V LVCMOS
  • SSTL-12
  • HSTL-12
  • POD12
  • HSUL-12
  • Differential SSTL-12
  • Differential HSTL-12
  • Differential HSUL-12
  • Differential POD-12
  • True Differential Signaling
GPIO Intel FPGA IP You can instantiate the GPIO Intel FPGA IP and customize the IP design using parameter editor in the Intel® Quartus® Prime software.
  • SDR transfer
  • DDIO transfer
  • Programmable open-drain output
  • Output enable
  • OCT