Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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5.2.2. Use High-Speed Clock from PLL to Clock SERDES Only

The high-speed clock generated from the PLL is intended to clock the SERDES circuitry only. Do not use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is restricted by the PLL FOUT specification.

For more information about the FOUT specification, refer to the Intel® Agilex™ Device Data Sheet.