Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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1.3.1. I/O Buffer and Registers in Intel® Agilex™ Devices

I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to the output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization. Use the GPIO Intel FPGA IP to utilize these registers to implement DDR circuitry.

The input and output paths contain the following blocks:
  • Input registers—support half/full rate data transfer from peripheral to the core, and support double or single data rate data captured from I/O buffer.
  • Output registers—support half/full rate data transfer from core to peripheral, and support double or single data rate data transfer to I/O buffer.
  • OE registers—support the output enable signal from core to the periphery, and double data rate / single data rate data transfer to I/O buffer.
The input and output paths also support the following features:
  • Clock enable
  • Asynchronous or synchronous reset
  • Bypass mode for input and output paths
  • Delay chain on input and output paths
Figure 3. IOE Structure for Intel® Agilex™ Devices

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