Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1.2. I/O Standards Implementation based on VCCIO_PIO Voltages

The following guidelines apply to I/O standards based on the VCCIO_PIO voltages.


When using 1.2 V VCCIO_PIO, you can implement singled-ended non-voltage-referenced and voltage-referenced I/O standards. This buffer also supports differential voltage-referenced I/O and true differential input standards with this voltage. You can implement a mix of both voltage-referenced and non-voltage-referenced I/O, and true differential input standards within the I/O bank.


When using 1.5 V VCCIO_PIO voltage, you can only implement true differential I/O standards. The buffer can interface with upstream or downstream devices that are compatible with the electrical specification of Intel® Agilex™ devices, specified in the Intel® Agilex™ Device Data Sheet. Analyze the electrical specification requirement to implement your true differential receiver. Implement DC coupling when the signal swing and offset voltage requirement is bounded within the Intel® Agilex™ True Differential Signaling standard specification. Otherwise, implement AC coupling and external bias circuitry.