Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents Synchronizer (DPA FIFO)

The synchronizer is a one-bit wide and six-bit deep FIFO buffer that compensates for the phase difference between dpa_fast_clock from the DPA block and the fast_clock that the I/O PLLs produce. The synchronizer can only compensate for phase differences, not frequency differences, between the data and the receiver’s input reference clock.

An optional port, rx_fifo_reset, is available to the internal logic to reset the synchronizer. The synchronizer is automatically reset when the DPA first locks to the incoming data. Use rx_fifo_reset to reset the synchronizer when the data checker indicates that the received data is corrupted.

Note: The synchronizer circuit is bypassed in non-DPA and soft-CDR mode.

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