Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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2.4.2.2.1. Generating the GPIO Intel FPGA IP ( Intel® Quartus® Prime Pro Edition)

Double-click the GPIO Intel FPGA IP in the IP Catalog to launch the parameter editor. The parameter editor allows you to define a custom variation of the IP. The parameter editor generates the IP variation synthesis and optional simulation files, and adds the .ip file representing the variation to your project automatically.

Follow these steps to locate, instantiate, and customize the IP in the parameter editor:

  1. Create or open an Intel® Quartus® Prime project (.qpf) to contain the instantiated IP variation.
  2. In the IP Catalog (Tools > IP Catalog), locate and double-click the GPIO Intel FPGA IP to customize.
  3. Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file named <your_ip> .ip. Click OK. The parameter editor appears.
    Figure 13.  GPIO Intel FPGA IP Parameter Editor
  4. Set the parameter values in the parameter editor and view the block diagram for the component. The Parameterization Messages tab at the bottom displays any errors in IP parameters.
  5. Click Generate HDL. The Generation dialog box appears.
  6. Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
  7. To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
  8. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
  9. Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
  10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

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