Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide
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Visible to Intel only — GUID: eei1550471789270
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2.1.2. Intel® Agilex™ I/O Buffer Behavior
GPIO Pin State | |||||
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Not turned on | Powering up | Fully powered up | Configuration mode | User mode | Powering down |
Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower. |
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All pins are tri-stated with weak pull-up enabled. |
All pins are tri-stated with weak pull-up enabled. | Valid data transactions can be initiated. |
|
SDM I/O Pin State | ||||
---|---|---|---|---|
Not turned on | Powering up | Fully powered up | Configuration mode | Powering down |
Pin voltage must not exceed VCCIO_SDM . |
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Refer to the related information. | Refer to the related information. |
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HPS I/O Pin State | |||||
---|---|---|---|---|---|
Not turned on | Powering up | Fully powered up | HPS initialization | HPS boot completed | Powering down |
Pin voltage must not exceed VCCIO_HPS . |
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All pins are configured as Schmitt Trigger input with 20 kΩ weak pull-up enabled. | All pins are configured as Schmitt Trigger input with 20 kΩ weak pull-up enabled. | Valid data transactions can be initiated. |
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