Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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2.1.2. Intel® Agilex™ I/O Buffer Behavior

Table 3.  GPIO I/O Pins Guideline for Different Pin States
GPIO Pin State
Not turned on Powering up Fully powered up Configuration mode User mode Powering down

Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower.

  • Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower.
  • After full VCC power up, the pins are tri-stated with weak pull-up enabled.

All pins are tri-stated with weak pull-up enabled.

All pins are tri-stated with weak pull-up enabled.

Valid data transactions can be initiated.

  • Pin voltage must not exceed VCCIO_PIO or 1.2 V, whichever is lower.
  • When the VCCIO_PIO and VCC power rails are powering down, the I/O pin signals measure between ground and the VCCIO_PIO voltage levels.
Table 4.  SDM I/O Pins Guideline for Different Pin States
SDM I/O Pin State
Not turned on Powering up Fully powered up Configuration mode Powering down

Pin voltage must not exceed VCCIO_SDM .

  • Pin voltage must not exceed VCCIO_SDM .
  • All pins are in undetermined state, except these pins:
    • VSIGP_0
    • VSIGP_1
    • VSIGN_0
    • VSIGN_1
    • RREF_SDM
Refer to the related information. Refer to the related information.
  • Pin voltage must not exceed VCCIO_SDM .
  • All pins are in undetermined state, except these pins:
    • VSIGP_0
    • VSIGP_1
    • VSIGN_0
    • VSIGN_1
    • RREF_SDM
Table 5.  HPS I/O Pins Guideline for Different I/O Pin States
HPS I/O Pin State
Not turned on Powering up Fully powered up HPS initialization HPS boot completed Powering down

Pin voltage must not exceed VCCIO_HPS .

  • Pin voltage must not exceed VCCIO_HPS .
  • All pins are in undetermined state.
All pins are configured as Schmitt Trigger input with 20 kΩ weak pull-up enabled. All pins are configured as Schmitt Trigger input with 20 kΩ weak pull-up enabled.

Valid data transactions can be initiated.

  • Pin voltage must not exceed VCCIO_HPS .
  • All pins are in undetermined state.
Note: After the Intel® Agilex™ device is fully powered up, input signals of the I/O pins must not exceed the maximum DC input voltage specification as specified in the Intel® Agilex™ Device Data Sheet.

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