Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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2.2.1. Programmable Output Slew Rate Control

Each I/O pin contains a slew rate control, allowing you to specify the slew rate on a pin-by-pin basis. The slew rate control affects both the rising and falling edges of the signal.

For GPIO pins implementation, Intel® Agilex™ devices support only the fast slew rate setting for voltage-referenced I/O standards. For 1.2 V LVCMOS I/O standard, you can select between fast, medium, and slow slew rate settings.

For external memory interface pins implementation, Intel® Agilex™ devices support fast, medium, and slow slew rate settings when you instantiate the EMIF Intel FPGA IP in your design.

A faster slew rate provides high-speed transitions for high-performance systems while a slower slew rate reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.

Note: Intel recommends that you perform IBIS or SPICE simulations to determine the best slew rate setting for your specific application.

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