5.1.7. External Memory Interface Pin Placement Requirements
Within an I/O bank, the top sub-bank is placed near the edge of the die, and the bottom sub-bank is placed near the FPGA core.
There are interconnects between the sub-banks which chain the sub-banks into a row. The following figures show the examples of how I/O lanes in various sub-banks are chained together to form the top and bottom I/O rows in various device variants. These figures represent the top view of the silicon die that corresponds to a reverse view of the device package.
The two sub-banks within an I/O bank are adjacent to each other, unless any of the sub-banks is not bonded out or partially bonded out. The blue line in the above figures shows the connectivity between the sub-banks.
For example, in the top row in Intel® Agilex™ AGF012 and AGF014 devices:
- The top sub-bank in 3A is adjacent to the bottom sub-bank in 3A and the bottom sub-bank in 3B.
- The top sub-bank in 3B is adjacent to the bottom sub-bank in 3B and the top sub-bank in 3C.
- The top sub-bank in 3B is adjacent to the top sub-bank in 3C even though there is a zipper block between the two sub-banks.
- The top sub-bank in 3B is not adjacent to the bottom sub-bank in 3A.
You can identify where a pin is located within an I/O bank based on its Index within I/O Bank value in the device pinout file.
For more information about sub-bank ordering for other Intel® Agilex™ device variants, refer to the External Memory Interfaces Intel® Agilex™ FPGA IP User Guide.
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