Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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2.2.4. Programmable Bus-Hold

Intel® Agilex™ devices support the programmable bus-hold feature on 1.2 V LVCMOS output. Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the configuration.

The bus-hold circuitry uses a resistor to weakly pull the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next input signal is present. Therefore, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.

For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent over-driving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the VCCIO_PIO level.

If you enable the bus-hold feature, you cannot use the programmable pull-up option.