- Updated the topic about the I/O buffer behavior to add more details on the power up, power down, and turned off conditions.
- Updated the guidelines for I/O pins in GPIO, HPS, and SDM banks during power sequencing.
- Added a section listing the I/O standards and features for configuration pins in different configuration schemes.
- Removed the table listing the configuration pin I/O standards and features.
- Updated the package selection and I/O vertical migration information.
- Updated the topic about programmable de-emphasis:
- The de-emphasis effect now affects signals at 1 UI or 0.5 UI depending on the interface clock frequency.
- Restructured the content for easier reference.
- Updated the GPIO IP version to 21.0.0.
- Removed NCSim support.
||Updated the diagram that shows the simplified view of the single-ended GPIO input path to update dout to dout and dout to dout.
- Updated the vertical migration table:
- Removed the AGF 004 product line.
- Removed the F1149A, R1615A, R2013A, R2470A, R3179C, R2581A, R3179B, and R3179A packages.
- Added R1546A, R2340A, R3184C, F2581A, R3184B, and R3184A packages.
- Removed H-tile and 3 V I/O support.
- Removed the Intel® Agilex™ AGF 014 FPGA.
- Updated default settings for the POD-12 and Differential POD-12 I/O standards from "High" to "Off".
- Added a topic about the Schmitt Trigger input buffer feature.
- Added assignment settings for the Schmitt Trigger input buffer.
- Added support for assigning 0 V, 1.2 V, or 1.5 V to the VCCIO_PIO pin in unused I/O banks.
- Updated the figures showing the I/O bank structure to improve clarity and to remove 3 V I/O.
- Updated the IP version for the GPIO and LVDS SERDES IPs to 20.0.0.
- Added 3 V H-tile I/O information in the following topics:
- General-purpose I/O and LVDS SERDES Overview.
- Intel® Agilex™ I/O and Differential I/O Buffers.
- I/O Banks.
- Supported I/O Standards.
- Programmable I/O Element (IOE) Features in Intel® Agilex™ Devices.
- Single-Ended I/O Standard OCT Termination.
- RS OCT.
- Single-ended I/O Standards External Termination.
- Input Path.
- GPIO Intel FPGA IP Architecture.
- Updated the voltage level of a pin signal during power down in the I/O Buffer Behavior.
- Updated the Supported Usage Modes with Number of IP Instances in an I/O Sub-bank table to clarified the maximum number of transmitter and receiver channels per IP instance.
- Updated lvds_clk and ext_lvds_clk signals width in the following tables:
- Example: Generating Output Clocks Using an IOPLL IP (Receiver in Non-DPA Mode).
- Example: Generating Output Clocks Using an IOPLL IP (Receiver in DPA or Soft-CDR Mode).
- Example: Generating Output Clocks Using a Shared IOPLL IP for Transmitter and Receiver Channels (Receiver in DPA or Soft-CDR Mode).
- Removed information about transmitter spanning across multiple I/O banks feature in the following topics:
- IOPLL Parameter Values for External PLL Mode.
- Intel® Agilex™ LVDS Interface with External PLL Mode.
- Updated the IOPLL IP settings in the Signal Interface between IOPLL and LVDS SERDES IPs table.
- Updated the Soft-CDR LVDS Receiver Interface with the IOPLL IP (with LVDS transmitter in the same sub-bank) figure.
- Added the following guideline topics in the I/O Design Guidelines chapter:
- Voltage Setting for Unused I/O Banks.
- Drive Strength Requirement for GPIO Input Pins.
- Observe Device Absolute Maximum Rating for 3.0 V Interfacing.
- Use Only One Voltage for All 3 V I/O Banks.
- Maximum True Differential Signaling RX Pairs Per I/O Lane.
- Do Not Drive 3 V I/O Pins During Power Sequencing.
- Updated LVDS SERDES Intel FPGA IP version to 19.5.0 with the following change:
- Improved the power usage of the IP.
- Removed the Duplex Feature parameter in the General Settings Tab table.
- Updated the condition for FPGA/PLL speed grade in the PLL Settings Tab table.
- Added short descriptions for General-purpose I/O Debug Guidelines and High-speed SERDES I/O Debug Guidelines tables.
- Changed R2560A name to R2581A in the Migration Capability Across Intel® Agilex™ Product Lines—Preliminary image.
- Clarified that programmable de-emphasis feature is only available when using Fast slew rate setting in the Programmable IOE Feature Settings for Intel® Agilex™ GPIO Bank table and Programmable De-Emphasis section.
- Added new GPIO Pins for Avalon-ST Configuration Scheme guideline topic.
- Added the Troubleshooting Guidelines topic.
- Added the following KDB links to the Transmitter Channel-to-Channel Skew and Receiver Skew Margin topics:
- Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?
- Why does the “TCCS Report” in LVDS SERDES Intel® FPGA IP SDC report an invalid TCCS value?
- Added the release notes links to the GPIO Intel FPGA IP Release Information, OCT Intel FPGA IP Release Information, and LVDS SERDES Intel FPGA IP Release Information topics.
- Updated the Programmable IOE Feature Settings for Intel® Agilex™ GPIO Bank table with default slew rate settings for GPIO and EMIF implementations.
- Updated the Programmable Output Slew Rate Control topic to specify different slew rate settings per design implementation.
- Removed recommendation to use HSPICE simulation to verify output voltages in th e Programmable Open-Drain Output topic.
- Updated guidelines in the External I/O Termination topic.
- Added the AC-Coupled External Termination for 1.2 V VCCIO_PIO figure in the External I/O Termination.
- Added the Simulation Models Descriptions table in the I/O Simulation topic.
- Updated OCT Intel FPGA IP and GPIO Intel FPGA IP connections for user mode calibration in the User Mode OCT topic.
- Added RZQ_GROUP QSF assignment description in the QSF Assignments table.
- Added OCT block and primitive I/O buffer connection figure in the QSF Assignments topic.
- Renamed the Guidelines for GPIO Pins During Power Sequencing section to Guidelines for I/O Pins in GPIO, HPS, and SDM Banks During Power Sequencing and updated the guidelines for GPIO, HPS, and SDM I/O pins in the section.
- Updated information about LVDS SERDES Intel FPGA IP version 19.4.0:
- Updated pll_areset signal connections in Non-DPA or DPA LVDS Receiver Interface with the IP (with LVDS transmitter in the same sub-bank), Soft-CDR LVDS Receiver Interface with the IP (with LVDS transmitter in the same sub-bank), and LVDS Transmitter Interface with the IP figures.
- Added description for ext_pll_locked signal in the External PLL Signals for LVDS SERDES IP and the Signal Interface between IOPLL and LVDS SERDES IPs tables.
- Added a note about the delay between the ext_pll_locked signal and the pll_locked signal assertions in the Initializing the LVDS SERDES IP in DPA Mode and the Initializing the LVDS SERDES IP in Non-DPA Mode topics.
- Updated information for GPIO Intel FPGA IP version 19.3.0:
- Changed seriesterminationcontrol and parallelterminationcontrol signals to terminationcontrol signal.
- Updated description on calibration block for mix I/O standards in the OCT Calibration Block topic.
- Added information about LVDS SERDES Intel FPGA IP version 19.3.0.
- Added Example of x4 DQ Groups with Shared OE, Reset, and Clock Enable Signals in Pinout Files figure in the Placement Requirements topic.
- Added Simultaneous Switching Noise and Clocking Requirements topics in the I/O Design Guidelines chapter.
- Added Placing LVDS Transmitters and Receivers in the Same I/O Bank and Using an External PLL topics in the LVDS SERDES Design Guidelines chapter.
- Added information to generate design example for OCT Intel FPGA IP version 19.3.0.
- Added Net Length Reports topic.
- Changed differential signaling naming from 1.5 V True Differential Signaling to True Differential Signaling.
- Added Input and Output columns for VCCIO_PIO voltage in the Intel® Agilex™ GPIO Bank Supported I/O Standards table.
- Added Intel® Quartus® Prime assignment names for each I/O standards.
- Added the following topics:
- I/O Buffer and Registers in Intel® Agilex™ Devices
- Configuring I/O Assignments in Intel® Quartus® Prime Software
- Configuring I/O Assignments Using Assignment Editor
- Configuring I/O Standards Using Pin Planner
- Configuring OCT Using Assignment Editor
- Configuring Differential Input RD OCT Using Assignment Editor
- Restructured the Intel® Agilex™ I/O Termination chapter.
- Updated default RS OCT calibration values in the Selectable I/O Standards for RS OCT table.
- Added explanation on the number of RS and RT OCT settings can a OCT calibration block supports for all I/O standards in OCT Calibration Block topic.
- Restructured the I/O and LVDS SERDES Design Guidelines chapter.
- Added the following diagrams in the Programmable De-Emphasis section:
- Signal Attenuation for De-emphasis Off for SSTL and HSTL I/O Standards
- Signal Attenuation for Constant Impedance De-emphasis for SSTL and HSTL I/O Standards
- Signal Attenuation for Low Power De-emphasis for SSTL and HSTL I/O Standards
- Signal Attenuation for De-emphasis Off for POD12 I/O Standard
- Signal Attenuation for Low Power De-emphasis for POD12 I/O Standard
- Removed maximum DC current restrictions for Intel® Agilex™ devices in the Maximum DC Current Restrictions topic.
- Added the OCT Calibration Block Requirement topic in Intel® Agilex™ I/O Design Guidelines.
- Added new restrictions about using AVSTx16 or AVSTx32 configuration scheme in SDM Shared I/O Requirements topic.
- Changed maximum VREF pin leakage current from 4 µA to 8 µA.
- Added information about GPIO Intel FPGA IP version 19.3.0.
- Added information about OCT Intel FPGA IP version 19.3.0.