Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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Document Table of Contents

2.4.2.2.2. GPIO Intel® FPGA IP Parameter Settings

You can set the parameter settings for the GPIO IP in the Intel® Quartus® Prime software. There are three groups of options: General, Buffer, and Registers.
Table 18.   General
Parameter Condition Values Default Description
Data Direction
  • Input
  • Output
  • Bidir
Output

Specifies the data direction for the GPIO.

Data width

1 to 128

4

Specifies the data width.

Use legacy top-level port names
  • On
  • Off
Off

Use the same port names as in Stratix® V, Arria® V, and Cyclone® V devices.

For example, dout becomes dataout_h and dataout_l, and din becomes datain_h and datain_l.

Note: The behaviors of these ports are different than in the Stratix® V, Arria® V, and Cyclone® V devices. For the migration guideline, refer to the related information.
Table 19.   GPIO IP Core Parameters - Buffer
Parameter Condition Values Default Description
Use differential buffer
  • On
  • Off
Off

If turned on, enables differential I/O buffers.

Use pseudo differential buffer
  • Data Direction = Output
  • Use differential buffer = On
  • On
  • Off
Off

If turned on in output mode, enables pseudo differential output buffers.

This option is automatically turned on for bidirectional mode if you turn on Use differential buffer.

Use bus-hold circuitry
  • Data Direction = Input or Bidir
  • Use differential buffer = Off
  • On
  • Off
Off

If turned on, the bus-hold circuitry can weakly hold the signal on an I/O pin at its last-driven state where the output buffer state is either 1 or 0 but not high-impedance.

Use open drain output
  • Data Direction = Output or Bidir
  • Use differential buffer = Off
  • On
  • Off
Off

If turned on, the open-drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system.

Enable output enable port Data Direction = Output
  • On
  • Off
Off

If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode.

Enable seriestermination / paralleltermination ports
  • On
  • Off
Off

If turned on, enables the terminationcontrol port of the output buffer to allow users to use user-mode OCT calibration.

Table 20.  Registers
Parameter Condition Values Default Description
Register mode
  • None
  • Simple register
  • DDIO
None Specifies the register mode for the GPIO IP:
  • None—specifies a simple wire connection from/to the buffer.
  • Simple register—specifies that the DDIO is used as a simple register in single data-rate mode (SDR). The Fitter may pack this register in the I/O.
  • DDIO— specifies that the IP uses the DDIO.
Enable synchronous clear / preset port
  • Register mode = DDIO
  • None
  • Clear
  • Preset
None

Specifies how to implement synchronous reset port.

  • None—Disables synchronous reset port.
  • Clear—Enables the SCLR port for synchronous clears.
  • Preset—Enables the SSET port for synchronous preset.
Enable asynchronous clear / preset port
  • Register mode = DDIO
  • None
  • Clear
  • Preset
None

Specifies how to implement asynchronous reset port.

  • None—Disables asynchronous reset port.
  • Clear—Enables the ACLR port for asynchronous clears.
  • Preset—Enables the ASET port for asynchronous preset.

ACLR and ASET signals are active high.

Enable clock enable ports Register mode = DDIO
  • On
  • Off
Off
  • On—exposes the clock enable (CKE) port to allow you to control when data is clocked in or out. This signal prevents data from being passed through without your control.
  • Off—clock enable port is not exposed and data always pass through the register automatically.
Half Rate logic Register mode = DDIO
  • On
  • Off
Off If turned on, enables half-rate DDIO. Refer to Input Path Waveform in DDIO Mode with Half-Rate Conversion figure in Input Path section.
Separate input / output Clocks
  • Data Direction = Bidir
  • Register mode = Simple register or DDIO
  • On
  • Off
Off If turned on, enables separate clocks (CK_IN and CK_OUT) for the input and output paths in bidirectional mode.