Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.2.2.2.2. LVDS SERDES IP PLL Settings

Table 53.  PLL Settings Tab
Parameter Condition Value Default Description
Use external PLL Specify additional output clocks based on existing PLL = Off On, Off Off

Turn on to use an external PLL:

  • The IP does not instantiate a local PLL.
  • The IP creates a series of clock connections with the "ext" prefix. Connect these ports to an externally generated PLL.
  • For details about how to configure the external PLL, refer to the Clock Resource Summary tab of the parameter editor.

This option allows you to access all of the available clocks from the PLL and use advanced PLL features such as clock switchover, bandwidth presets, dynamic phase stepping, and dynamic reconfiguration.

Desired inclock frequency   100.0 Specifies the inclock frequency in MHz.
Actual inclock frequency The value changes according to the Desired inclock frequency parameter input. Displays the closest inclock frequency to the desired frequency that can source the interface.
FPGA/PLL speed grade The value changes according to the selected device part number. Specifies the FPGA/PLL speed grade which determines the operation range of the PLL.
Enable pll_areset port Always enabled On Exposes the pll_areset port. You can use the pll_areset signal to reset the entire LVDS interface.
Core clock resource type Periphery Specifies onto which clock network the IP exports an internally generated coreclock.

The clock network resource type is always set to periphery.

Specify additional output clocks based on existing PLL Use external PLL = Off On, Off Off Exports additional PLL output clocks based on the existing PLL settings. You can only specify output clocks that are not currently used internally to the IP; the output clocks that are used internally are not modifiable. Be cautious when doing cross clock domain transfer with exported output clocks because these output clocks are asynchronous to other clocks generated by the IP.
Table 54.  PLL Settings Tab—Output Clocks
Parameter Condition Value Default Description
Number of Additional Clocks Specify additional output clocks based on existing PLL = On 0 – 4 0 Specifies the number of additional output clocks to be exposed.
Table 55.  PLL Settings Tab—outclk(n)In this table, n represents the number of output clocks starting with 0. Parameters for outclk0 to outclk4 are reserved. The modifiable parameters for the output clock start with outclk5 (pll_extra_clock0).
Parameter Condition Value Default Description
Desired frequency Number of Additional Clocks = 1 or 2 or 3 or 4 1.0 to 10000.0 100.0 Specifies the output clock frequency of the corresponding output clock port, pll_extra_clock[], in MHz.
Actual frequency Number of Additional Clocks = 1 or 2 or 3 or 4 Depends on the Desired frequency input. 100.0 Allows you to select the actual output clock frequency from a list of achievable frequencies.
Phase shift units Number of Additional Clocks = 1 or 2 or 3 or 4 ps ps Specifies the phase shift unit for the corresponding output clock port, pll_extra_clock[], in picoseconds (ps)
Phase shift Number of Additional Clocks = 1 or 2 or 3 or 4 0.0 Specifies the requested value for the phase shift. The default value is 0 ps.
Actual phase shift Number of Additional Clocks = 1 or 2 or 3 or 4 Depends on the Phase shift input. 0.0 Allows you to select the actual phase shift from a list of achievable phase shift values. The default value is the closest achievable phase shift to the desired phase shift.
Desired duty cycle Number of Additional Clocks = 1 or 2 or 3 or 4 0 - 100 50.0 Specifies the requested value for the duty cycle in percentage.
Actual duty cycle Number of Additional Clocks = 1 or 2 or 3 or 4 Depends on the Desired duty cycle input. 50.0 Allows you to select the actual duty cycle from a list of achievable duty cycle values in percentage. The default value is the closest achievable duty cycle to the desired duty cycle.

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