Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Generating the OCT Intel FPGA IP ( Intel Quartus® Prime Pro Edition)

Double-click the OCT Intel FPGA IP in the IP Catalog to launch the parameter editor. The parameter editor allows you to define a custom variation of the IP. The parameter editor generates the IP variation synthesis and optional simulation files, and adds the .ip file representing the variation to your project automatically.

Follow these steps to locate, instantiate, and customize the IP in the parameter editor:

  1. Create or open an Intel® Quartus® Prime project (.qpf) to contain the instantiated IP variation.
  2. In the IP Catalog (Tools > IP Catalog), locate and double-click the OCT Intel FPGA IP to customize.
  3. Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file named <your_ip> .ip. Click OK. The parameter editor appears.
    Figure 37.  OCT Intel FPGA IP Parameter Editor
  4. Set the parameter values in the parameter editor and view the block diagram for the component. The Parameterization Messages tab at the bottom displays any errors in IP parameters.
  5. Click Generate HDL. The Generation dialog box appears.
  6. Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
  7. To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
  8. To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
  9. Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
  10. After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.

OCT Intel FPGA IP Parameter Settings

Table 42.   OCT Intel® FPGA IP Parameters
Name Value Description
Number of OCT blocks 1 to 12 Specifies the number of OCT blocks to be generated. The default value is 1.
OCT mode
  • Power-up
  • User
Specifies whether OCT is user-controllable or not. The default value is Power-up.

IP Core Generation Output ( Intel Quartus Prime Pro Edition)

The Intel® Quartus® Prime software generates the following output file structure for individual IPs that are not part of a Platform Designer system.
Figure 38. Individual IP Generation Output ( Intel® Quartus® Prime Pro Edition)

Table 43.  Output Files of Intel® FPGA IP Generation
File Name Description
<your_ip>.ip Top-level IP variation file that contains the parameterization of an IP in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a .qsys file.
<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files.
<your_ip>_generation.rpt IP or Platform Designer generation log file. Displays a summary of the messages during IP generation.
<your_ip>.qgsimc (Platform Designer systems only) Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP. This comparison determines if Platform Designer can skip regeneration of the HDL.
<your_ip>.qgsynth (Platform Designer systems only) Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP. This comparison determines if Platform Designer can skip regeneration of the HDL.
<your_ip>.csv Contains information about the upgrade status of the IP component.
<your_ip>.bsf A symbol representation of the IP variation for use in Block Diagram Files (.bdf).
<your_ip>.spd Input file that ip-make-simscript requires to generate simulation scripts. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize.
<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner.
<your_ip>_bb.v Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox.
<your_ip>_inst.v or _inst.vhd HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<your_ip>.regmap If the IP contains register information, the Intel® Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console.

Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system.

During synthesis, the Intel® Quartus® Prime software stores the .svd files for slave interface visible to the System Console masters in the .sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system slaves, Platform Designer accesses the registers by name.



HDL files that instantiate each submodule or child IP for synthesis or simulation.
mentor/ Contains a msim_setup.tcl script to set up and run a ModelSim* simulation.
aldec/ Contains a Riviera-PRO* script rivierapro_setup.tcl to setup and run a simulation.



Contains a shell script to set up and run a VCS* simulation.

Contains a shell script and synopsys_sim.setup file to set up and run a VCS* MX simulation.

/xcelium Contains an Xcelium* Parallel simulator shell script and other setup files to set up and run a simulation.
/submodules Contains HDL files for the IP submodule.
<IP submodule>/ Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates.

OCT Intel FPGA IP Signals

Table 44.  Input Interface SignalsIn the table, n represents the number of OCT blocks defined in the Number of OCT blocks parameter.
Signal Name Direction Width Description
rzqin[n:0] Input 1 per OCT block Input connection from RZQ pad to the OCT block. RZQ pad is connected to an external resistance. The OCT block uses impedance connected to the rzqin port as a reference to generate the calibration code.

This signal is available for power-up and user modes.

calibration_request[n:0] Input 1 per OCT block Set to 1 to request the OCT block to start calibration. Hold the signal for at least 2 ms or until ack_recal is set to 1.

This signal is only available for user mode.

ack_recal[n:0] Output 1 per OCT block When set to 1 indicates OCT block is ready for calibration. There should be no calibration activities from the core to the OCT block until this signal is asserted for every calibration request.

This signal is only available for user mode.

ser_data_n Output 1 per OCT block Transfer serial output calibration data from OCT block to I/O buffer.

QSF Assignments

Intel® Agilex™ devices support the following termination-related Intel® Quartus® Prime settings file (.qsf) assignments:

Table 45.  QSF Assignments
QSF Assignment Details


The input/output termination assignment specifies the termination value in ohm on the pin in question.


set_instance_assignment -name INPUT_TERMINATION <value> -to <pin name>
set_instance_assignment -name OUTPUT_TERMINATION <value> -to <pin name>

To enable the series/parallel termination ports, include these assignments, which specify the series and parallel termination values for the pins.

Make sure to connect the ser_data port from the OCT Intel® FPGA IP to the GPIO Intel® FPGA IP.

set_instance_assignment -name INPUT_TERMINATION "PARALLEL <VALUE> OHM WITH CALIBRATION" -to <pin>
set_instance_assignment -name OUTPUT_TERMINATION "SERIES <VALUE> OHM WITH CALIBRATION" -to <pin>

Directs the Fitter to make the proper connection from the desired OCT block to the specified pins. This assignment is useful when I/O buffers are not explicitly instantiated and you need to associate the pins with a specific OCT block.


set_instance_assignment -name TERMINATION_CONTROL_BLOCK <desired OCT BLK> -to <pin name>

The Fitter searches for the rzq pin name in the netlist. If the pin does not exist, the Fitter creates the pin name along with the OCT IP and its corresponding connections. This allows you to create a group of pins to be calibrated by an existing or non-existing OCT and the Fitter ensures the legality of the design.


set_instance_assignment -name RZQ_GROUP <rzq pin name> -to <pin name>

Termination can exist on input and output buffers, and sometimes simultaneously.

There are two methods to associate pin groups with an OCT block:

  • Use a .qsf assignment to indicate which pin (bus) is associated with which OCT block. You can use the TERMINATION_CONTROL_BLOCK assignment to associates a pin with an OCT instantiated in the RTL.
  • Instantiate the I/O buffer primitives at the top level and connect them to the appropriate OCT blocks as shown in the following figure.
    Figure 39. OCT Block Connection with I/O Buffer
Note: All I/O banks within the same bank row with the same VCCIO can share one OCT block even if that particular I/O bank has its own OCT block. You can connect any number of I/O pins that support calibrated termination to an OCT block. Ensure that you connect I/Os with compatible configuration to an OCT block. You must also ensure that the OCT block and its corresponding I/Os have the same VCCIO and series or parallel termination values. With these settings, the Fitter places the I/Os and OCT block in the same column. The Intel® Quartus® Prime software generates warning messages if there is no pin connected to the block.

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