Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents

5.1.10. SDM Shared I/O Requirements

The AvSTx16 and AvSTx32 configuration modes use the configuration pins located in a GPIO bank for device configuration. The GPIO bank is powered by 1.2 V VCCIO_PIO instead of 1.8 V VCCIO_SDM. Refer to the Intel® Agilex™ Configuration User Guide for more details on the I/O setting of the pins during device configuration.

When you use AVSTx16/x32 configuration scheme, AVST pins in the SDM shared IO bank are not usable as user I/Os for:

  • Designs using external partial reconfiguration, for example, send partial reconfiguration bitstream using AVST pins.
  • Designs using HPS.