Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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Document Table of Contents

4.2.2.2.1. LVDS SERDES IP General Settings

Table 52.  General Settings Tab
Parameter Condition Value Default Description
Functional mode
  • TX
  • RX Non-DPA
  • RX DPA-FIFO
  • RX Soft-CDR
TX

Specifies the functional mode of the interface.

Number of channels

Disable the Enable tx_outclock port parameter to select 12 channels TX design.

  • 1 to 12 for TX
  • 1 to 12 for RX Non-DPA
  • 1 to 12 for RX DPA-FIFO
  • 1 to 8 for RX Soft-CDR
1

Specifies the number of serial channels in the interface.

  • If you use a dedicated reference clock for the TX, RX non-DPA, RX DPA-FIFO or RX DPA-CDR, you must use one of the channels for the refclk pin. Use a dedicated reference clock to reduce jitter.

For an LVDS RX design, place the refclk pin on the same I/O bank as the receiver.

Data rate 150.0 to 1600.0 1000.0 Specifies the data rate (in Mbps) of a single serial channel. The data rate follows the I/O PLL VCO operating range and the maximum data rate is dependent on the device core speed grade. Refer to the Intel® Agilex™ Device Data Sheet data rate operating range for each core speed grade.
SERDES factor 3, 4, 5, 6, 7, 8, 9, and 10 10 Specifies the serialization rate or deserialization rate for the LVDS interface.
Use backwards-compatible port names On, Off Off Turn on to use legacy top-level names that are compatible with the ALTLVDS_TX and ALTLVDS_RX IPs.

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