Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.1.2. Intel® Agilex™ GPIO Banks, SERDES, and DPA Locations

The I/O banks are located at the top and bottom I/O rows respectively. Each I/O bank contains two I/O sub-banks and each I/O sub-bank contains its own PLL, dynamic phase alignment (DPA), and SERDES circuitry blocks.
Figure 50. I/O Bank Structure with I/O PLL, DPA, and SERDES (Top View)This diagram shows the I/O bank structure of the Intel® Agilex™ AGI 027 device. Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks for each device package.

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