Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents DPA Mode

The DPA block chooses the best possible clock (dpa_fast_clock) from the eight fast clocks produced by the I/O PLL.

The serial dpa_fast_clock signal is used for writing serial data into the synchronizer. The serial fast_clock signal is used for reading serial data from the synchronizer, data realignment, and deserializer blocks.

In DPA mode, the DPA FIFO synchronizes the re-timed data to the high-speed SERDES clock domain. The DPA clock may shift phase during the initial lock period. To avoid data run-through condition caused by the FIFO write pointer creeping up to the read pointer, hold the FIFO in reset state until the DPA locks.

Figure 70. Receiver Datapath in DPA Mode This figure shows the DPA mode datapath. In the figure, all the receiver hardware blocks are active.
Note: In DPA mode, you must place all receiver channels of a SERDES instance in one I/O sub-bank. Because each I/O sub-bank has a maximum of 12 True Signaling I/O buffer receiver pairs, each SERDES instance can support a maximum of 12 DPA channels.