Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.7.1. Transmitter Channel-to-Channel Skew

The receiver skew margin calculation uses the transmitter channel-to-channel skew (TCCS)—an important parameter based on the Intel® Agilex™ transmitter in a source-synchronous differential interface:

  • TCCS is the difference between the fastest and slowest data output transitions, including the TCO variation and clock skew.
  • For SERDES transmitters, the Timing Analyzer provides the TCCS value in the TCCS report (report_TCCS) in the Intel® Quartus® Prime compilation report, which shows TCCS values for serial output ports.
  • You can also get the TCCS value from the device data sheet.

Perform PCB trace compensation to adjust the trace length of each SERDES channel to improve channel-to-channel skew when interfacing with non-DPA receivers at the data rate above 840 Megabits per second (Mbps). The Intel® Quartus® Prime software Fitter Report panel reports the amount of delay you must add to each trace. You can use the recommended trace delay numbers shown under the Transmitter/Receiver Package Skew Compensation panel and manually compensate the skew on the PCB board trace to reduce channel-to-channel skew, thus meeting the timing budget between SERDES channels.

Did you find the information on this page useful?

Characters remaining:

Feedback Message