Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.1.4. Single-ended I/O Termination Implementation Guide

To implement I/O termination in your design, you can use the Intel® Quartus® Prime software to assign the termination for your pins or instantiate an OCT Intel FPGA IP.

Did you find the information on this page useful?

Characters remaining:

Feedback Message