Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1. Intel® Agilex™ General-Purpose I/O and LVDS SERDES Overview

Updated for:
Intel® Quartus® Prime Design Suite 21.3
The Intel® Agilex™ I/O system includes a general-purpose I/O (GPIO) interface, a Secure Device Manager (SDM) I/O interface, and a Hard Processor System (HPS) I/O interface. Each I/O interface is designed to meet different interfacing requirements.
The general-purpose I/O interface system support:
  • 1.2 V single-ended non-voltage referenced Joint Electron Device Engineering Council (JEDEC) compliant I/O standards.
  • 1.2 V single-ended and differential voltage referenced JEDEC compliant I/O standards.
  • True differential I/O compatible with LVDS and able to interface with LVDS subsets such as RSDS, Mini-LVDS, Sub-LVDS, and any I/O standards that use equivalent electrical specification.
  • DDR4 memory interface up to 1600 MHz with a Hard Memory Controller (HMC).
  • LVDS serializer/deserializer (SERDES) interface up to 1.6 Gbps.

The SDM and HPS I/O interfaces can support 1.8 V single-ended non-voltage referenced I/O standard for SDM and HPS interfacing.

Did you find the information on this page useful?

Characters remaining:

Feedback Message