Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.5.1. IOPLL IP Signal Interface with LVDS SERDES IP

Table 72.  Signal Interface between IOPLL and LVDS SERDES IPs This table lists the signal interface between the output ports of the IOPLL IP and the input ports of the LVDS SERDES IP transmitter or receiver.
From the IOPLL IP To the LVDS SERDES IP transmitter or receiver
lvds_clk[1:0] (serial clock output signal)
  • Configure this signal using outclk0 in the PLL.
  • Select Enable LVDS_CLK/LOADEN 0 & 1 option for the Access to PLL LVDS_CLK/LOADEN output port setting.

The serial clock output can only drive ext_lvds_clk[1:0] on the LVDS SERDES IP transmitter and receiver. This clock cannot drive the core logic.

ext_lvds_clk[1:0] (serial clock input to the transmitter or receiver)

loaden[1:0] (load enable output)

  • Configure this signal using outclk1 in the PLL.
  • Select Enable LVDS_CLK/LOADEN 0 & 1 option for the Access to PLL LVDS_CLK/LOADEN output port setting.

ext_loaden[1:0] (load enable to the transmitter or receiver)

outclk4 (parallel clock output)

ext_coreclock (core clock to the LVDS SERDES Intel FPGA IP)

locked

ext_pll_locked

This signal indicates when external PLL is locked. It does not indicate if SERDES is ready for initialization.

reset

pll_areset (asynchronous PLL reset port)

phout[7:0]

  • This signal is required if ext_vcoph[7:0] is required.

  • Configure this signal by turning on Specify VCO frequency in the PLL and specifying the VCO frequency value.
  • Turn on Enable access to PLL DPA output port.

ext_vcoph[7:0]

This signal is required for all transmitter or receiver modes.

Did you find the information on this page useful?

Characters remaining:

Feedback Message