Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents Using an External PLL

  • To use an external PLL, in the LVDS SERDES IP parameter editor, turn on the Use external PLL option.
  • You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter.
  • In each instance, you can use up to the following number of channels:
    • 12 transmitters
    • 12 DPA or non-DPA receivers
    • 8 soft-CDR receivers
  • Generate the IOPLL Intel FPGA IP and ensure that the .qsf file lists the IOPLL IP before the LVDS SERDES IP. This order is required for your design to compile with the proper clock constraints.
  • Connect the same PLL to both the transmitter and receiver instances. You can either use the tx_coreclock from the LVDS transmitter instance or the rx_coreclock from the LVDS receiver instance to clock your core logic. For RX Soft-CDR mode, connect the tx_coreclock of the LVDS transmitter instance to the ext_coreclock port of the LVDS receiver instance.
  • Set the I/O standard for refclk port of the IOPLL IP to be compatible with the I/O standard used by the LVDS SERDES IP.

Refer to the Connection between IOPLL IP and LVDS SERDES IP in External PLL Mode section for LVDS SERDES IP with external PLL mode connection guidelines.