Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents GPIO Intel® FPGA IP Design Examples

The GPIO IP can generate design examples that match your IP configuration in the parameter editor. You can use these design examples as references for instantiating the IP and reviewing the expected behavior in simulations.

You can generate the design examples from the GPIO IP parameter editor. After setting the parameters that you want, click Generate Example Design. The IP generates the design example source files in the directory you specify.

Figure 30. Source Files in the Generated Design Example Directory

Note: The .qsys files are for internal use during design example generation only. You cannot edit these .qsys files.