Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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5.2.3. Pin Placement for Differential Channels

Each GPIO sub-bank contains its own PLL. A PLL can drive all receiver and transmitter channels in the same sub-bank. However, the individual PLL cannot drive receiver and transmitter channels in another I/O sub-bank. You must use the dedicated clock pins to drive the LVDS PLLs.

The pin index number 0-47 and pin index number 48-95 from device pin out files are respectively assigned to bottom sub-bank and top sub-bank in a single GPIO bank.

Refer to External Memory Interface Pin Placement Requirements for more information about the sub-bank arrangement for each I/O bank.

PLLs Driving DPA-Enabled Differential Receiver Channels

For differential receivers, the PLL can drive all channels in the same I/O sub-bank but cannot drive across banks.

Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.

DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel® Quartus® Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.

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