Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.6. LVDS SERDES IP Initialization and Reset

During device initialization, the clock reference must be stable while the PLL is locking to it to avoid corruption of the PLL output clock phase shifts. If the PLL output clock phase shifts are incorrect, data transfer between the high-speed LVDS and low-speed parallel domain can fail and causes corrupted data.

After you have initialized the IP in DPA or non-DPA mode, you can perform word boundaries alignment using the bitslip control signal.

Note: Intel requires you to include the Reset Release Intel® FPGA IP in your design to hold your application logic in the reset state until the entire FPGA fabric is in user mode. For more information about the Reset Release Intel® FPGA IP, refer to the Intel Agilex Configuration User Guide: Including the Reset Release Intel FPGA IP in Your Design in the related information.

Did you find the information on this page useful?

Characters remaining:

Feedback Message