Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.1.1. High-Speed SERDES Architecture

Each GPIO bank in Intel® Agilex™ devices consists of two I/O sub-banks. Each I/O sub-bank consists of the following components:
  • 12 pairs of dedicated SERDES transmitter channels.
  • 12 pairs of dedicated SERDES receiver channels that support DPA and non-DPA modes. Four pairs from the top sub-bank and eight pairs from the bottom sub-bank dedicated SERDES receiver channels support Soft-CDR mode. Refer to the Intel® Agilex™ device pin-out files for the exact location of the Soft-CDR pins.

The SERDES transmitter and receiver channels are adjacent to each other. Refer to the Intel® Agilex™ device pin-out files for the exact location of the SERDES pins.

Figure 48.  Intel® Agilex™ I/O Subsystem (Top View)This diagram shows the I/O bank structure of the Intel® Agilex™ AGI 027 device. Different device packages have different number of I/O banks. Refer to the device pin-out files for available I/O banks for each device package.
Figure 49. SERDES CircuitryThis figure shows a transmitter and receiver block diagram for the SERDES circuitry with the interface signals of the transmitter and receiver data paths. The figure shows a transmitter and a receiver sharing an I/O PLL as they are in the same sub-bank and using the same I/O PLL resource. In single data rate (SDR) and double data rate (DDR) modes, the data widths are 1 and 2 bits, respectively.
Table 49.  Supported Blocks and Modes for Data and Clock Path
Path Mode Block Clock Domain
TX Data Path TX Serializer SERDES clock domain
RX Data Path DPA-FIFO DPA DPA clock domain
Synchronizer DPA-SERDES clock domain crossing
Bitslip SERDES clock domain
Deserializer SERDES clock domain
Soft-CDR DPA DPA clock domain
Bitslip DPA clock domain
Deserializer DPA clock domain
Non-DPA DPA Not used
Synchronizer Not used
Bitslip SERDES clock domain
Deserializer SERDES clock domain

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