Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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7. Documentation Related to the Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

The following links are references related to the Intel® Agilex™ GPIO, OCT, and LVDS SERDES system.
Table 84.   References
Reference Description
Intel® Agilex™ Device Data Sheet

This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Agilex™ devices.

Intel® Agilex™ Device Family Pin Connection Guidelines

This document describes guidelines for all the pins in Intel® Agilex™ devices.

Intel® Agilex™ Clocking and PLL User Guide

This document describes the Intel® Agilex™ clock and PLL specifications and guidelines.

Intel® Agilex™ Configuration User Guide

This document describes the Intel® Agilex™ configuration specifications and guidelines.

Intel® Agilex™ Power Management User Guide This document describes Intel® Agilex™ power management specifications and guidelines.
IBIS Models for Intel Devices

This link provides IBIS models for Intel® Agilex™ devices.

AN 433: Constraining and Analyzing Source-Synchronous Interfaces This application note describes techniques for constraining and analyzing source-synchronous interfaces.
GPIO Intel FPGA IP Release Notes This release notes lists the changes made in each release of the GPIO Intel FPGA IP.
OCT Intel FPGA IP Release Notes This release notes lists the changes made in each release of the OCT Intel FPGA IP.
LVDS SERDES Intel FPGA IP Release Notes This release notes lists the changes made in each release of the LVDS SERDES Intel FPGA IP.

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