Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.5. Intel® Agilex™ LVDS Interface with External PLL Mode

The LVDS SERDES IP parameter editor provides an option for implementing the LVDS interface with the Use External PLL option. With this option enabled you can control the PLL settings, such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings.

If you enable the Use External PLL option with the LVDS SERDES IP transmitter and receiver, the following signals are required from the IOPLL Intel® FPGA IP:

  • Serial clock (fast clock) input to the SERDES of the LVDS SERDES IP transmitter and receiver
  • Load enable to the SERDES of the LVDS SERDES IP transmitter and receiver
  • Parallel clock (core clock) used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
  • Asynchronous PLL reset port of the LVDS SERDES IP receiver
  • PLL VCO signal for the DPA and soft-CDR modes of the LVDS SERDES IP receiver

The Clock Resource Summary tab in the LVDS SERDES IP parameter editor provides the details for the signals in the preceding list.

You must instantiate an IOPLL IP to generate the various clocks and load enable signals. Configure these settings in the IOPLL IP parameter editor:

  • Set the Compensation Mode option in the PLL tab according to the following table
  • Set the Output Clocks options in the PLL tab
  • Set Access to PLL LVDS_CLK/LOADEN output port option to Enable LVDS_CLK/LOADEN 0 & 1 in the Settings tab
Table 71.  Compensation Mode Setting to Generate IOPLL IPWhen you generate the IOPLL IP, use the PLL setting in this table for the corresponding LVDS functional mode.
LVDS Functional Mode IOPLL IP Setting
TX, RX DPA, RX Soft-CDR Direct mode
RX non-DPA LVDS compensation mode