Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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4.3.1. LVDS SERDES Transmitter Blocks

The dedicated circuitry consists of a true differential buffer, a serializer, and I/O PLLs that you can share between the SERDES transmitter and receiver. The serializer takes up to 10 bits wide parallel data from the FPGA fabric. It clocks the data into the load registers, and serializes the data using shift registers that are clocked by the I/O PLL sending the data to the differential buffer. The MSB of the parallel data is transmitted first.

Note: The PLL that drives the SERDES channel must operate in integer PLL mode. You do not need a PLL if you bypass the serializer.
Figure 53. LVDS SERDES Transmitter
Table 67.  Dedicated Circuitry and Features of the LVDS SERDES Transmitter
Dedicated Circuitry / Feature Description
Differential I/O buffer Supports True Differential Signaling I/O standard which is compatible with LVDS, RSDS, and Mini-LVDS.
SERDES 3 to 10-bit wide serializer
Phase-locked loops (PLLs) Clocks the load and shift registers
Programmable VOD Adjusts the output voltage swing
Programmable pre-emphasis Boosts output current

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