Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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Document Table of Contents

3.1.4.2. Using OCT Intel FPGA IP for I/O Termination Implementation

The OCT Intel® FPGA IP allows you to dynamically calibrate I/O with reference to an external resistor. The OCT IP improves signal integrity, reduces board space, and is necessary for communicating with external devices such as memory interfaces.

The OCT IP supports the following features:

  • Support for up to 12 on-chip termination (OCT) blocks
  • Support for calibrated on-chip series termination (RS) and calibrated on-chip parallel termination (RT) on all I/O pins
  • Support dynamically switching between series termination (RS) and parallel termination (RT)
  • Support for OCT calibration in power-up and user modes
  • Support double calibration for DDR4 and non-DDR4 applications