Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021

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Document Table of Contents GPIO Intel® FPGA IP Architecture

The GPIO IP supports the GPIO components and features of Intel® Agilex™ device family. You can use the Intel® Quartus® Prime parameter editor to configure the GPIO IP.

Components of the GPIO IP:

  • Double data rate input/output (DDIO)—halves or doubles the data-rate of a communication channel
  • Delay chains—configure the delay chains to perform specific delay and assist in I/O timing closure
  • I/O buffers—connect the pads to the FPGA