Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1.4. Placement Requirements

I/O Pins Placement Restrictions

The following are the pin placement requirements for Intel® Agilex™ devices:
  • Only DQS pins support differential voltage referenced input standard.
  • Each x4 DQ group shares the same OE, Reset, and clock enable signals, therefore you cannot split the OE, Reset or clock enable signals within a x4 DQ group. Refer to the Intel® Agilex™ device pin-out files for more information on DQ groups. Refer to the GPIO Intel® FPGA IP Interface Signals section for a list of OE, Reset, and clock enable signals.
Figure 86. Example of OE, Reset, and Clock Enable Signals Sharing for x4 DQ Group in Pinout Files

I/O Pins Placement Guidelines

The following are guidelines for I/O standard selection and I/O bank supply compatibility check:
  • Select a suitable signaling type and I/O standard for each I/O pin. The I/O banks are located in rows along the top and bottom periphery of the device. Each I/O sub-bank contains its own PLL, DPA and SERDES circuitry.
  • Ensure that the selected I/O standard is supported in the targeted I/O bank.
  • Place I/O pins that share voltage levels in the same I/O bank.
  • Verify that all output signals in each I/O bank are intended to drive out at the bank's I/O voltage level.
  • Verify that all voltage referenced signals in each I/O bank are intended to use the bank's VREF voltage level.

Did you find the information on this page useful?

Characters remaining:

Feedback Message