Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.1.20.1. HSPICE* Models

Intel® Agilex™ devices provide a SPICE model that you can use to perform system-level simulations for various configurations.
The SPICE kits provide models that support a wide variety of I/O features across process, voltage, and temperature (PVT). Each SPICE kit contains the following information:
  • Encrypted transistor and logic cell library models
  • Encrypted input or output buffer circuit models for single-ended and differential I/O
  • Single-ended and differential sample SPICE decks
  • User guide describing the model usage
The HSPICE* models provide options to simulate buffer behavior for following I/O feature:
  • RS OCT with and without calibration
  • RT OCT with calibration
  • Internal weak pull-up
  • Open drain
  • Bus-hold

Did you find the information on this page useful?

Characters remaining:

Feedback Message