Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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Document Table of Contents

Figure 18.  High-Level View of Single-Ended GPIO


Table 28.   GPIO IP Data Path Modes
Data Path Register Mode
Bypass Simple Register DDR I/O
Full-Rate Half-Rate
Input Data goes from the delay element to the core, bypassing all double data rate I/Os (DDIOs). The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data.
Output Data goes from the core straight to the delay element, bypassing all DDIOs. The full-rate DDIO operates as a simple register, bypassing half-rate DDIOs. The Fitter chooses whether to pack the register in the I/O or implement the register in the core, depending on the area and timing trade-offs. The full-rate DDIO operates as a regular DDIO, bypassing the half-rate DDIOs. The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate data.
Bidirectional The output buffer drives both an output pin and an input buffer. The full-rate DDIO operates as a simple register. The output buffer drives both an output pin and an input buffer. The full-rate DDIO operates as a regular DDIO. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops. The full-rate DDIO operates as a regular DDIO. The half-rate DDIOs convert full-rate data to half-rate. The output buffer drives both an output pin and an input buffer. The input buffer drives a set of three flip-flops.

If you use asynchronous clear and preset signals, all DDIOs share these same signals.

Half-rate and full-rate DDIOs connect to separate clocks. When you use half-rate and full-rate DDIOs, the full-rate clock must run at twice the half-rate frequency. You can use different phase relationships to meet timing requirements.

Input Path

The pad sends data to the input buffer, and the input buffer feeds the delay element. After the data goes to the output of the delay element, the programmable bypass multiplexers select the features and paths to use.

Each input path contains two stages of DDIOs, which are full-rate and half-rate.

Figure 19. Simplified View of Single-Ended GPIO Input Path


  1. The pad receives data.
  2. DDIO IN (1) captures data on the rising and falling edges of ck_fr and sends the data, signals (A) and (B) in the following waveform figure, at single data rate.
  3. DDIO IN (2) and DDIO IN (3) halve the data rate.
  4. dout[3:0] presents the data as a half-rate bus.
Figure 20. Input Path Waveform in DDIO Mode with Half-Rate Conversion

In this figure, the data goes from full-rate clock at double data rate to half-rate clock at single data rate. The data rate is divided by four and the bus size is increased by the same ratio. The overall throughput through the GPIO IP remains unchanged.

The actual timing relationship between different signals may vary depending on the specific design, delays, and phases that you choose for the full-rate and half-rate clocks.



Note: The GPIO IP does not support dynamic calibration of bidirectional pins.

Output and Output Enable Paths

The output delay element sends data to the pad through the output buffer.

Each output path contains two stages of DDIOs, which are half-rate and full-rate.

Figure 21. Simplified View of Single-Ended GPIO Output Path


Figure 22. Output Path Waveform in DDIO Mode with Half-Rate Conversion
Figure 23.  Simplified View of Output Enable Path


The difference between the output path and output enable (OE) path is that the OE path does not contain full-rate DDIO. To support packed-register implementations in the OE path, a simple register operates as full-rate DDIO. For the same reason, only one half-rate DDIO is present.

The OE path operates in the following three fundamental modes:

  • Bypass—the core sends data directly to the delay element, bypassing all DDIOs.
  • Packed Register—bypasses half-rate DDIO.
  • SDR output at half-rate—half-rate DDIOs convert data from full-rate to half-rate.
Note: The GPIO IP does not support dynamic calibration of bidirectional pins.

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