Intel® Agilex™ General-Purpose I/O and LVDS SERDES User Guide

ID 683780
Date 10/29/2021
Public

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2.1.1. Supported I/O Standards

The VCCIO_PIO, VCCPT, and VCC power supplies power to the Intel® Agilex™ GPIO buffers. The VCCIO_SDM power supply powers the SDM I/O buffer and the VCCIO_HPS power supply powers the HPS I/O buffer. Each I/O bank has its own power supply and supports only one I/O voltage.
The following table shows the supported I/O standards for GPIO, HPS, and SDM I/O banks.
Table 1.   Intel® Agilex™ I/O Standards Support per I/O Bank TypeThe True Differential Signaling I/O standard is compatible with the LVDS, RSDS, Mini-LVDS, and LVPECL standards at a lower signal swing. Refer to the Intel® Agilex™ Device Data Sheet for the electrical specifications of the True Differential Signaling I/O standard.
I/O Standard GPIO Bank HPS I/O Bank SDM I/O Bank
1.8 V LVCMOS No Yes Yes
1.2 V LVCMOS Yes No No
SSTL-12 Yes No No
HSTL-12 Yes No No
HSUL-12 Yes No No
POD12 Yes No No
Differential SSTL-12 Yes No No
Differential HSTL-12 Yes No No
Differential HSUL-12 Yes No No
Differential POD12 Yes No No
True Differential Signaling Yes No No
The True Differential Signaling input buffer can be placed in a GPIO bank powered by 1.2 V and 1.5 V VCCIO_PIO. The maximum input voltage to the True Differential Signaling input buffer must not exceed the value based on the calculation maximum VICM + (maximum VID/2):
  • For 1.5V VCCIO_PIO bank, the maximum input voltage is 1.7 V.
  • For 1.2V VCCIO_PIO bank, the maximum input voltage is 1.4 V

By default, the Intel® Quartus® Prime software assigns 1.2 V to the VCCIO_PIO pin in unused I/O banks. To assign 0 V, 1.2 V, or 1.5 V I/O standards to the pin, specify the assignment in the .qsf file.

Refer to the Intel® Agilex™ Device Data Sheet for the True Differential Signaling I/O standard electrical specifications.

The following table shows the input and output voltages for a GPIO I/O bank.

Table 2.   Intel® Agilex™ GPIO Bank Supported I/O Standards
I/O Standard VCCIO_PIO (V) VCCPT (V) Vref (V) VTT (V) JEDEC Standard
Input Output
1.2 V LVCMOS 1.2 1.2 1.8 - - JESD-12A.01
SSTL-12 1.2 1.2 1.8 0.6 0.6 JESD79-4B
HSTL-12 1.2 1.2 1.8 0.6 0.6 JESD-16A
HSUL-12 1.2 1.2 1.8 0.6 - JESD209-3C
POD12 1.2 1.2 1.8 Internally calibrated 1.2 JESD79-4B
Differential SSTL-12 1 1.2 1.2 1.8 - 0.6 JESD79-4B
Differential HSTL-121 1.2 1.2 1.8 - 0.6 JESD8-16A
Differential HSUL-121 1.2 1.2 1.8 - - JESD209-3C
Differential POD-121 1.2 1.2 1.8 Internally calibrated 1.2 JESD79-4B
True Differential Signaling2 1.2/1.5 1.5 1.8 - - -
1 Uses two single-ended outputs with second output programmed as inverted.
2 True Differential Signaling input buffers are powered by 1.8 V VCCPT

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